View 24LC174_3058134.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1995 microchip technology inc. ds21101c-page 1 features single supply with operation down to 2.5v 16 bytes otp secure memory low power cmos technology - 1 ma active current typical - 10 m a standby current typical at 5.5v -5 m a standby current typical at 3.0v organized as 8 blocks of 256 bytes (8 x 256 x 8) two wire serial interface bus, i 2 c ? compatible functional address inputs for cascading up to 8 devices schmitt trigger, ?tered inputs for noise suppression output slope control to eliminate ground bounce 100 khz (2.5v) and 400 khz (5v) compatibility self-timed write cycle (including auto-erase) page-write buffer for up to 16 bytes 2 ms typical write cycle time for page-write hardware write protect for entire memory can be operated as a serial rom factory programming (qtp) available esd protection > 4,000v 10,000,000 erase/write cycles guaranteed data retention > 200 years 8 pin dip, 8-lead soic packages available for extended temperature ranges - commercial: 0 c to +70 c - industrial: -40 c to +85 c description the microchip technology inc. 24LC174 is a cascad- able 16k bit electrically erasable prom. the device is organized as 8 blocks of 256 x 8 bit memory with a two wire serial interface and provides a specially addressed otp (one-time programmable) 16 byte security block. low voltage design permits operation down to 2.5 volts with standby and active currents of only 5 m a and 1 ma respectively. the 24LC174 also has a page-write capability for up to 16 bytes of data. the 24LC174 is available in the standard 8-pin dip and 8-lead surface mount soic packages. the three select pins, a0, a1, and a2, function as chip select inputs and allow up to eight devices to share a common bus, for up to 128k bits total system eeprom. package type block diagram dip 8-lead soic 1 2 3 4 8 7 6 5 v wp scl sda cc a0 a1 a2 v ss 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v wp scl sda cc 24LC174 24LC174 hv generator eeprom array (8 x 256 x 8) page latches ydec xdec sense amp r/w control memory control logic i/o control logic wp sda scl v cc v ss a0 a2 a1 24LC174 16k 2.5v cascadable cmos serial eeprom with otp security page this document was created with framemaker 4.0.4
24LC174 ds21101c-page 2 1995 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ........................................................................ 7.0v all inputs and outputs w.r.t. v ss ..... -0.3v to vcc +1.0v storage temperature ...........................-65?c to +150?c ambient temp. with power applied ......-65?c to +125?c soldering temperature of leads (10 seconds) ...+300?c esd protection on all pins ......................................3 4 kv * notice: stresses above those listed under ?aximum ratings?may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function v ss ground sda serial address/data i/o scl serial clock wp write protect input v cc +2.5v to 5.5v power supply a0, a1, a2 chip address inputs table 1-2: dc characteristics figure 1-1: bus timing start/stop vcc = +2.5v to 5.5v commercial (c): tamb = 0?c to +70?c industrial (i): tamb = -40?c to +85?c parameter symbol min max units conditions wp, scl and sda pins: high level input voltage low level input voltage hysteresis of schmitt trigger inputs low level output voltage v ih v il v hys v ol .7 v cc .05 v cc .3 v cc .40 v v v v note 1 i ol = 3.0 ma, v cc = 2.5v input leakage current i li -10 10 m av in = .1v to v cc output leakage current i lo -10 10 m av out = .1v to v cc pin capacitance (all inputs/outputs) c in , c out ?0 pfv cc = 5.0v (note1), tamb = 25 c, f clk = 1 mhz operating current i cc write i cc read 3 1 ma ma v cc = 5.5v, scl = 400 khz standby current i ccs 30 100 m a m a v cc = 3.0v, sda = scl = v cc v cc = 5.5v, sda = scl = v cc note 1: this parameter is periodically sampled and not 100% tested. scl sda start stop t su:sta t hd:sta t su:sto v hys
1995 microchip technology inc. ds21101c-page 3 24LC174 table 1-3: ac characteristics figure 1-2: bus timing data parameter symbol standard mode v cc= 4.5 - 5.5v fast mode units remarks min max min max clock frequency f clk 100 400 khz clock high time t high 4000 600 ns clock low time t low 4700 1300 ns sda and scl rise time t r 1000 300 ns note 2 sda and scl fall time t f 300 300 ns note 2 start condition hold time t hd : sta 4000 600 ns after this period the ?st clock pulse is generated start condition setup time t su : sta 4700 600 ns only relevant for repeated start condition data input hold time t hd : dat 00ns data input setup time t su : dat 250 100 ns stop condition setup time t su : sto 4000 600 ns output valid from clock t aa 3500 900 ns note 1 bus free time t buf 4700 1300 ns time the bus must be free before a new transmission can start output fall time from v ih min to v il max t of 250 20 +0.1 c b 250 ns note 2, c b 100 pf input ?ter spike suppres- sion (sda and scl pins) t sp 50 50 ns note 3 write cycle time t wr 10 10 ms byte or page mode note 1: as a transmitter, the device must provide an internal minimum delay time to bridge the unde?ed region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. note 2: not 100% tested. c b = total capacitance of one bus line in pf. note 3: the combined t sp and v hys speci?ations are due to new schmitt trigger inputs which provide improved noise and spike suppression. this eliminates the need for a t i speci?ation for standard operation. su:sta t hd:sta t f t low t high t r t su:sto t buf t t aa t sda out sda in scl hd:dat t su:dat t aa sp t
24LC174 ds21101c-page 4 1995 microchip technology inc. 2.0 functional description the 24LC174 supports a bidirectional two wire bus and data transmission protocol. a device that sends data onto the bus is de?ed as transmitter, and a device receiving data as receiver. the bus has to be con- trolled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the 24LC174 works as slave. both, master and slave can operate as transmitter or receiver but the master device deter- mines which mode is activated. 3.0 bus characteristics the following bus protocol has been de?ed: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been de?ed (see figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data t ransfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condi- tion. 3.3 stop data t ransfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data v alid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last six- teen will be stored when doing a write operation. when an overwrite does occur it will replace data in a ?st in ?st out fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges, has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24LC174) will leave the data line high to enable the master to generate the stop condition. note: the 24LC174 does not generate any acknowledge bits if an internal program- ming cycle is in progress. figure 3-1: data transfer sequence on the serial bus scl sda (a) (b) (d) (d) (c) (a) start condition address or acknowledge valid data allowed to change stop condition
1995 microchip technology inc. ds21101c-page 5 24LC174 4.0 bus characteristics 4.1 device addressing and operation a control byte is the ?st byte received following the start condition from the master device. the ?st bit is always a one. the next three bits of the control byte are the device select bits (a2, a1, a0). they are used to select which of the eight devices are to be accessed. the a1 bit must be the inverse of the a1 device select pin. the next three bits of the control byte are the block select bits (b2, b1, b0). they are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. these bits are in effect the three most signi?ant bits of the word address. the last bit of the control byte de?es the operation to be performed. when set to one a read operation is selected, when set to zero a write operation is selected. following the start condition, the 24LC174 looks for the slave address for the device selected. depending on the state of the r/w bit, the 24LC174 will select a read or write operation. figure 4-1: control byte allocation operation control code block select r/w read 1 a2 a1 a0 block address 1 write 1 a2 a1 a0 block address 0 start read/write slave address r/w 1 a2a1a0b2b1b0 a msb lsb 5.0 write operation 5.1 byte w rite following the start condition from the master, the device code (4 bits), the block address (3 bits), and the r/w bit which is a logic low is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will fol- low after it has generated an acknowledge bit during the ninth clock cycle. therefore the next byte transmit- ted by the master is the word address and will be writ- ten into the address pointer of the 24LC174. after receiving another acknowledge signal from the 24LC174 the master device will transmit the data word to be written into the addressed memory location. the 24LC174 acknowledges again and the master gener- ates a stop condition. this initiates the internal write cycle, and during this time the 24LC174 will not gener- ate acknowledge signals (see figure 5-1). 5.2 page w rite the write control byte, word address and the ?st data byte are transmitted to the 24LC174 in the same way as in a byte write. but instead of generating a stop con- dition the master transmits up to sixteen data bytes to the 24LC174 which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order seven bits of the word address remains constant. if the master should transmit more than six- teen words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (see figure 8-1). figure 5-1: byte write s t o p sda line p data s t a r t control byte s word address bus activity: master bus activity: a c k a c k a c k 1 a2 b0 a1 a0 b2 b1
24LC174 ds21101c-page 6 1995 microchip technology inc. 6.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 6-1 for ?w dia- gram. figure 6-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes 7.0 write protection the 24LC174 can be used as a serial rom when the wp pin is connected to vcc. programming will be inhibited and the entire memory will be write-protected. 8.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, ran- dom read, and sequential read. 8.1 current address read the 24LC174 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24LC174 issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24LC174 discontin- ues transmission (see figure 9-1). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, ?st the word address must be set. this is done by sending the word address to the 24LC174 as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24LC174 will then issue an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24LC174 dis- continues transmission (see figure 9-2). figure 8-1: page write s t o p sda line p data n s t a r t control byte word address (n) bus activity: master bus activity: a c k a c k a c k data n + 1 a c k data n + 15 a c k s a2 b0 a1 a0 b2 b1
1995 microchip technology inc. ds21101c-page 7 24LC174 8.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24LC174 transmits the ?st data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24LC174 to transmit the next sequentially addressed 8 bit word (see figure 9-3). to provide sequential reads the 24LC174 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows an entire device memory contents to be serially read during one operation. 8.4 noise protection the 24LC174 employs a vcc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and ?ter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 9.0 pin descriptions 9.1 sda serial address/data input/output this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pullup resistor to v cc (typical 10k w for 100 khz, 1k w for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 9.2 scl serial clock this input is used to synchronize the data transfer from and to the device. 9.3 wp this pin must be connected to either v ss or v cc . if tied to v ss , normal memory operation is enabled (read/write the entire memory 000-7ff). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read opera- tions are not affected. this feature allows the user to use the 24LC174 as a serial rom when wp is enabled (tied to vcc). 9.4 a0, a1, a2 these pins are used to con?ure the proper chip address in multiple-chip applications (more than one 24LC174 on the same bus). the levels on these pins are compared to the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight 24LC174s may be connected to the same bus. these pins must be connected to either v ss or v cc . 9.5 security access control the security row is enabled by sending the control sequence with the i 2 c slave address of 0110. bit 0 of the control byte must be set to a 1 for a read oper- ation or a 0 for the otp write operation. the security access data is always read starting at byte 0 for n bytes up to and including byte 15. (see figure 9-3). 9.6 security access w rite the s.a.w. data is written to the device using a normal page write following the proper control access sequence. upon receiving the ?al stop bit, the internal write sequence will commence. at the completion of the internal write sequence a fuse will be set disabling the write function for the 16 byte security page. 9.7 security access read the security access read is accomplished by executing the normal read sequences, following the security access control sequence with bit 0 set to a 1. the secu- rity page read starts at data byte 0. note: the level on a1 is compared to the inverse of the slave address.
24LC174 ds21101c-page 8 1995 microchip technology inc. figure 9-1: current address read figure 9-2: random read figure 9-3: sequential read figure 9-4: security control byte allocation control a c k s t a r t s t o p byte data n bus activity master sda line bus activity a c k n o s 1 a2 a1 a0 b2 b1 b0 p s t o p sda line s t a r t control byte word address (n) bus activity: master bus activity: a c k a c k a c k data n s t a r t control byte s n o a c k s 1 a2 b0 a1 a0 b2 b1 p s t o p sda line data n data n + 1 bus activity: master bus activity: a c k a c k a c k data n + 2 a c k p data n + x control byte n o a c k operation control code mbz r/w read 0110 000 1 write 0110 000 0 start read/write slave address r/w 0110000 a msb lsb
1995 microchip technology inc. ds21101c-page 9 24LC174 figure 9-5: security page read figure 9-6: security page write s t o p sda line data 1 data 2 bus activity: master bus activity: a c k a c k data 3 a c k p data 15 control byte sda line control byte word address (n) bus activity: master bus activity: a c k a c k control byte a c k data 0 s t a r t r/ w 0 0 01 1 s 0 01 1 s s t a r t 1 a c k r/ w sda line control byte word address (n) bus activity: master bus activity: a c k a c k s t a r t 0 0 01 1 s r/ w s t o p data n a c k data n + 1 a c k p data n + 15
24LC174 ds21101c-page 10 1995 microchip technology inc. notes:
1995 microchip technology inc. ds21101c-page 11 24LC174 notes:
24LC174 ds21101c-page 12 1995 microchip technology inc. 24LC174 product identi cation system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales of?es. package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead temperature blank = 0?c to +70?c range: i = -40?c to +85?c device: 24LC174 16k cmos serial eeprom 24LC174t 16k cmos serial eeprom (tape and reel) 24LC174 - /p americas (continued) san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 9/5/95 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/biz/mchip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. 35 rockridge road englewood, oh 45322 tel: 513 832-2543 fax: 513 832-2841 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 "information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. use of microchip's products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights." the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. printed in the usa, 9/95 1995, microchip technology incorporated

▲Up To Search▲

Price & Availability of 24LC174

	To Download 24LC174 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .